1. Technical Field
Present invention embodiments relate to processing service requests, and more specifically, to processing interrupt service requests (ISRs) for hardware accelerators utilized in parallel processing in an efficient manner.
2. Discussion of the Related Art
Hardware accelerators, e.g., Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), etc., may be utilized in computing systems to offload work performed by a Central Processing Unit (CPU) to improve computing performance. Accelerators may communicate with the CPU via an interface (e.g., a Peripheral Component Interconnect Express (PCIe) bus, PCI bus, other high-speed bus interface, etc.). Typically, interrupts are used to communicate the status of processing events between the hardware accelerator and CPU. Memory Mapped Input Output (MMIO) requests, which may be used to read registers across a bus, may be utilized to read interrupt requests stored at a physical memory location on the accelerator.
Software-based processes for managing interrupt requests typically involve an interrupt request being sent from a processing core of the hardware accelerator to the CPU. The interrupt request is acknowledged, and registers of the hardware accelerator corresponding to the interrupt are read by the CPU. The CPU also writes to the registers to clear interrupt requests that have been received. Such processes may involve multiple communications between the CPU and the hardware accelerator.
As the number of processing cores (engines) in accelerators has increased from 1 or 2 cores to 4, 8, 16 or more cores, managing interrupt signals has become more complicated and time consuming. For example, each core is associated with a set of interrupt signals, and one or more MMIO requests may be needed to read each set of interrupt signals from a single processing core. In some cases, a first register corresponding to an interrupt is read in order to determine which other registers pertaining to the interrupt need to be read, thus resulting in multiple MMIO read requests over the bus. MMIO requests are slow in operation, and as the number of cores increase, the number of MMIO requests also increase, which adversely impacts system performance. For example, while interrupts are being processed, accelerator cores are not performing work, and thus, acceleration capabilities of the hardware accelerator are underutilized.